1. Field of the Invention
The invention relates generally to sputtering of materials in the fabrication of semiconductor integrated circuits. In particular, the invention relates to ionized copper sputtering.
2. Background Art
Copper is rapidly replacing aluminum as the preferred metallization in advanced semiconductor integrated circuits. Metallization is used to form electrical interconnects extending horizontally in usually multiple wiring levels and extending vertically between wiring levels. Such vertical interconnects are usually called vias. Similar vertical connections to an underlying silicon layer are usually called contacts and require additional barriers and contact layers, but for purposes of this invention, they may be considered as vias. Copper is advantageous for metallization because, among other reasons, it has a lower electrical resistivity and is less subject to electromigration than aluminum. It is understood that the copper used for metallization need not be pure but may be advantageously doped with alloying elements such as magnesium and aluminum or other intentional or unintentional dopants to less than 10 wt %. Copper presents challenges as well as the stated advantages over aluminum.
Aluminum etching techniques are well developed to define the horizontal wiring and to restrict the aluminum to the via area, but copper has proven to be difficult if not impossible to etch in a commercial environment. Instead, damascene processes have been developed. As illustrated in the cross-sectional view of FIG. 1, a lower-level dielectric layer 10 is typically formed of a material based on an oxide of silicon, hence its common name of oxide layer. Conductive features 12, 13, such as copper features, in a surface of the lower-level dielectric layer 10. An inter-level dielectric layer 14 is deposited as a planar layer over the lower-level dielectric layer 10 and its conductive features 12, 13. In the case of single damascene, a via hole 16 is etched through the inter-level dielectric layer 14 over the conductive feature 12 to be electrically contacted. In the case of dual damascene, a more complex hole is etched including a via hole 18 in the lower portion of inter-level dielectric layer 14 and a wider trench 20 in its upper part connected to the via hole 18. While the via holes 16, 18 typically have a circular shape of minimum width, approximately 0.13 μm in current advanced technology, and provide the vertical interconnects, the trench 20 has a larger rectangular shape that may extend a significant distance perpendicularly to the plane of illustration to provide a horizontal interconnect perhaps contacting multiple conductive features in the lower-level dielectric layer 14 as well as providing conductive features or pads to a yet higher level of wiring. The etching of the complex dual-damascene structure of the trench 20 and connected via 18 may be done in a number of well known ways, typically involving an unillustrated etch stop layer, for example, of silicon nitride formed midway in the inter-level dielectric layer 14. The same wiring level may include both single-damascene vias 16 and the dual-damascene via 18 and trench 20, which are simultaneously etched and filled.
Direct contact of copper to oxide should be avoided. Copper can diffuse into the oxide potentially causing electrical shorts through the dielectric material. Oxygen can diffuse into the copper reducing its electrical conductivity. Hence, a thin conformal barrier layer 22 is coated onto the sides of the via holes 16, 18 and trench 20 though it is preferably removed from the bottom of the via holes 16, 18 to reduce contact resistance to the conductive features 12, 13. For copper metallization, tantalum nitride (TaN) is the preferred barrier material that blocks the diffusion of either copper or oxygen through it, but a tantalum layer is sometimes first deposited to improve adhesion to the oxide. Other barrier materials, typically involving a refractory nitride such as TiN or WN, have been suggested, and more complex barrier structures than a Ta/TaN bilayer have also been suggested.
The fundamental concept in a damascene process is that the metal, here copper, is deposited to not only fill the via holes 16, 18 and the trench 20 but also over the top surface 24 of the inter-level dielectric layer 14. Chemical mechanical polishing (CMP) is then used to remove the copper extending above the level of the single-damascene via 16 and the dual-damascene trench 20. Because oxide is much harder than copper and has a different type of chemical bonding, the CMP process can be tuned to stop on the top oxide surface 24 after the overlying copper and usually the barrier material have been removed. As a result, the copper is confined to the vias 16, 18 and the trench 20.
The process for depositing copper faces the difficulty of filling via holes having high aspect ratios, that is, the ratio of depth to minimum width. As mentioned before, via widths of 0.13 μm represent current advanced technology, and further and significant decreases in the critical dimension are being planned. On the other hand, the thickness of the inter-level dielectric is constrained to be no less than about of 0.7 μm or even greater for more complex structures in order to avoid or minimize cross-talk and dielectric breakdown. Therefore, the aspect ratio of holes to be filled is 5 or greater, and this value will only increase in the future.
Sputtering a metal to fill such high aspect-ratio holes inherently presents difficulties since sputtering is fundamentally a ballistic process ill suited for reaching the bottom of such holes. As illustrated in the cross-sectional view of FIG. 2, if conventional techniques without further embellishments are used to sputter a copper layer 40 into a high-aspect hole 42 formed in a substrate 44, the copper preferentially deposits on the upper corners of the hole 42 to form overhangs 46, which eventually bridge over before the bottom of the hole 42 is filled. As a result, deleterious voids will form. Ionized sputtering, also called ion plating, is known in which a significant fraction of the sputtered copper atoms are ionized. If the wafer being coated is negatively biased, the positive copper ions can be drawn deeply into narrow holes. However, it has been conventionally felt that for sufficiently narrow holes ion plating will still produce excessive overhangs while reducing sputter deposition into the bottom of the high aspect-ratio holes with the resultant formation of voids. If the ion energy is increased too much to reduce the overhangs, the barrier layer at the corner may also be removed, thus exposing the copper to oxide with the accompanying deleterious results mentioned above.
Electro-chemical plating (ECP) has been significantly developed recently to perform the copper fill. ECP is a wet electrolytic process in which a liquid electrolyte containing copper ions flows into the narrow holes and deposits copper nearly conformally on the sides and bottoms of high aspect-ratio holes. ECP has several advantages beyond its conformality. It deposits relatively quickly and uses an inexpensive source of copper. However, ECP has several disadvantages. It is a wet process which is difficult to integrate with the dry plasma processing associated with most of the rest of semiconductor fabrication. Its incompatibility with dry room operation complicates the production queue. Further, since ECP is an electrolytic process depositing onto a dielectric under layer, it is necessary to provide an electrode layer over the dielectric. Nitrides in the barrier layer are insufficiently conducting for this purpose, and even the refractory metals exhibit poor conductivity. As a result, it is conventional to deposit a thin conformal copper seed layer on top of the barrier layer, which not only acts as a plating electrode but also nucleates the ECP copper while adhering to the nitride barrier. Ionized plating of copper performed on wafers held at less than 50° C. has proven effective at forming the copper seed layer. At a minimum, ionized sputtering, when used to form thin copper seed layers, is not so subject to overhangs because only such a small amount of copper needs to be deposited that is insufficient to produce bridging. However, its thickness must be great enough to uniformly cover the dielectric over the vertical extent of the hole. At via diameters of 0.13 μm and below, the combined thickness of the barrier layer and the copper seed layer further narrows the hole, increasing its effective aspect ratio. The copper seed deposition also introduces an additional process step.
Finally, ECP may not be sufficient for the very high aspect-ratio holes anticipated for 90 nm processing. If any overhangs exist from the barrier or seed layer deposition, the generally conformal ECP deposition may cause the top of the hole to bridge over before the bottom of the hole is filled, thereby creating voids in the via metallization. Further, ECP relies upon the flow of fresh electrolyte into the hole and the removal of depleted electrolyte from it. Since electrolyte replenishment is more effective at the top of the hole, ECP is likely to form its own overhangs which may close the hole before the hole is filled. That is, voids in the copper may still develop with ECP.
Ding et al. in U.S. Pat. No. 6,184,137 describe a copper fill procedure in which the fill is only incompletely performed such that a thin capillary is formed to extend vertically down the center of the via hole. The copper is then reflowed at above 450° C. to fill the capillary. Ding et al. in published European Patent Application EP 0 878 843 A2 describe a multi-step copper sputtering process involving different temperatures. Chiang et al. in U.S. Pat. No. 6,398,929 disclose a copper seed layer deposited by SIP followed by a higher-temperature sputter deposition of copper.
There is much prior art for cold/hot aluminum sputtering processes, but this work is not obviously transferrable to copper sputtering because copper's melting point of 1093° C. is much higher than the 660° C. of aluminum, the higher temperature being totally incompatible with previously formed structure such as shallow dopant implant profiles, thin gate oxides, and organic low-k dielectrics while the lower temperature is much closer to temperatures tolerable by these features.